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RS485EN
- RS485的双向通信处，正在为此头疼的同学们可要注意了，这个可以解决你们双向通信过程中的很多问题哦-Two-way RS485 communications, the headache is to this end they' ll pay attention to the students, this two-way communication you can solve many problems in the course of oh
RS_code
- ｒｓ纠错代码，采用ＶＨＤＬ实现，可以成为不错的参考。-rs error-correcting code, the use of VHDL implementation can be a good reference.
rs_enc
- 这是一个用VHDL编写的RS信道编码程序-This is a VHDL prepared with RS channel coding procedures
c_FPGA
- RS232设计，硬件测试通过，VERILOG实现的，比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
DVB
- DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
VHD
- RS编码中用到的交织和去交织程序，VHDL描述，交织深度8-nterlace with VHDL，depth is 8
rs232_transmit_control
- RS-232 transmir control programmed in VHDL
byzxin_RS232
- RS 232 interface vhdl language programme for video processing pcb board.
Trigger
- 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
asynchronous-sequential-circuits
- 利用基本RS触发器设计电平异步时序电路的方法 此文档帮助读者设计数字逻辑电路，并非VHDL语言实现-The use of the basic RS flip-flop design level asynchronous sequential circuits This document is to help readers design digital logic circuits, not the VHDL language
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,
091220111singalcpu
- 用verilog HDL语言或者VHDL语言来编写，实现单周期CPU的设计。能够完成以下十六条指定： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti
rs232
- this is vhdl code. purpose of rs-232 connected with altera cyclone2.
RS_coding_123
- RS编码的实现，包括C语言，C++，java，VHDL，DSP，matlab的RS编码实现，代码全部调是通过。-RS encoded, including the C language, C++, java, VHDL, DSPs, Matlab the RS coding, the code all the tune through.
rs232_receiver
- receiver RS-232 programmed in VHDL
rs422
- RS-422的VHDL实现，代码测试能用-RS-422 VHDL implementation code test can be used
188135a9844b
- rs(204,188)译码器VHDL语言源代码-failed to translate
82be270ea751
- RS（255，239）编码器的VHDL语言源代码，希望能对大家有一定帮助-the code of the encoder of rs（255,239），hope can help you